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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max5132/max5133 low-power, 13-bit, voltage-out- put digital-to-analog converters (dacs) feature an inter- nal precision bandgap reference and output amplifier. the max5132 operates on a single +5v supply with an internal reference of +2.5v and offers a configurable out- put amplifier. if necessary, the user can override the on- chip, <10ppm/? voltage reference with an external reference. the max5133 has the same features as the max5132 but operates from a single +3v supply and has an internal +1.25v precision reference. the user- accessible inverting input and output of the amplifier allows specific gain configurations, remote sensing, and high output drive capability for a wide range of force/sense applications. both devices draw only 500? of supply current, which reduces to 3? in power-down mode. in addition, their power-up reset feature allows for a user-selectable initial output state of either 0v or mid- scale and reduces output glitches during power-up. the serial interface is compatible with spi, qspi, and microwire, which makes the max5132/ max5133 suitable for cascading multiple devices. each dac has a double-buffered input organized as an input register followed by a dac register. a 16-bit shift register loads data into the input register. the dac register may be updated independently or simultaneously with the input register. both devices are available in a 16-pin qsop package and are specified for the extended-industrial (-40? to +85?) operating temperature range. for pin-compati- ble 14-bit upgrades, see the max5171/max5173 data sheet; for pin-compatible 12-bit versions, see the max5122/max5123 data sheet. applications industrial process control automatic test equipment (ate) digital offset and gain adjustment motion control microprocessor-controlled systems features ? single-supply operation +5v (max5132) +3v (max5133) ? built-in 10ppm/? max precision bandgap reference +2.5v (max5132) +1.25v (max5133) ? spi/qspi/microwire-compatible, 3-wire serial interface ? pin-programmable shutdown-mode and power- up reset (0v or midscale output voltage) ? buffered output capable of driving 5k ?? 100pf or 4?0ma loads ? space-saving 16-pin qsop package ? pin-compatible upgrades for the 12-bit max5122/max5123 ? pin-compatible 14-bit upgrades available (max5171/max5173) max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 fb v dd refadj ref agnd pd upo dout dgnd top view max5132 max5133 qsop out rstval cs pdl clr din sclk 19-1441; rev 0; 3/99 part max5132 aeee max5132beee -40? to +85? -40? to +85? temp. range pin- package 16 qsop 16 qsop pin configuration ordering information inl (lsb) ?.5 ? max5133 aeee max5133beee ? -40? to +85? -40? to +85? 16 qsop 16 qsop ? spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp.
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ax5132 (+5v) (v dd = +5v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, output amplifier connect- ed in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd, dgnd ...............................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v digital inputs to dgnd.............................................-0.3v to +6v digital outputs (dout, upo) to dgnd .....-0.3v to (v dd + 0.3v) fb, out to agnd ......................................-0.3v to (v dd + 0.3v) ref, refadj to agnd ..............................-0.3v to (v dd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 16-pin qsop (derate 8.00mw/? above +70?)..........667mw operating temperature range ..........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10sec) .............................+300? v in = 0 or v dd max5132a refadj = v dd 4.5v v dd 5.5v max5132b max5132b max5132a max5132a t a = +25? conditions pf 8 c in input capacitance ? -1 0.001 1 i in input leakage current mv 200 v hys input hysteresis v 0.8 v il input low voltage v 3 v ih input high voltage ? 3.3 7 refadj current ppm/? 10 tcv ref 3 output voltage temperature coefficient v 2.475 2.5 2.525 v ref output voltage -0.5 0.5 bits 13 n resolution ?/v 20 250 psrr power-supply rejection ratio ppm/? 10 30 tcv fs 310 full-scale temperature coefficient (note 3) lsb -1 1 dnl differential nonlinearity mv -10 10 v os offset error (note 2) -3 -0.2 3 mv ge gain error units min typ max symbol parameter i sink = 2ma i source = 2ma v 0.13 0.4 v ol output low voltage v v dd - 0.5 v oh output high voltage max5132b lsb -1 1 inl integral nonlinearity (note 1) 0 i out 100? (sourcing) ?/? 50 v out /i out reference external load regulation ma 4 reference short-circuit current static performance reference digital input digital outputs
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference _______________________________________________________________________________________ 3 electrical characteristics?ax5132 (+5v) (continued) (v dd = +5v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, output amplifier connect- ed in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) to ?.5lsb, v step = 2.5v cs = v dd , f sclk = 100khz, v sclk = 5vp-p conditions ? 320 i shdn power-supply current in shutdown ? 500 600 i dd power-supply current (note 5) v 4.5 5.5 v dd power-supply voltage (note 5) nv-s 5 digital feedthrough ms 2 time required to exit shutdown ? -0.1 0 0.1 current into fb ? 20 output settling time v 0 to v dd output voltage swing (note 4) units min typ max symbol parameter electrical characteristics?ax5133 (+3v) (v dd = +3v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, output amplifier connected in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) max5133a refadj = v dd 2.7v v dd 3.3v max5133b max5133b max5133a max5133a t a = +25? conditions mv 200 v hys input hysteresis v 0.8 v il input low voltage v 2.2 v ih input high voltage ? 3.3 7 refadj current ma 4 reference short-circuit current ppm/? 10 tcv ref max5133b 3 0 i out 100? (sourcing) output voltage temperature coefficient v 1.237 1.25 1.263 v ref output voltage -1 1 ?/? 0.1 1 bits 13 n resolution ?/v 20 250 psrr power-supply rejection ratio ppm/? 10 30 tcv fs lsb 310 v out /i out full-scale temperature coefficient (note 3) lsb -1 1 dnl differential nonlinearity mv -10 10 v os offset error (note 2) reference external load regulation mv -5 -0.2 5 ge gain error units min typ max symbol parameter -2 2 inl integral nonlinearity (note 1) v/? 0.6 sr voltage output slew rate dynamic performance power requirements static performance reference digital input
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference 4 _______________________________________________________________________________________ electrical characteristics?ax5133 (+3v) (continued) (v dd = +3v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, output amplifier connected in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) to ?.5lsb, v step = 1.25v cs = v dd , f sclk = 100khz, v sclk = 3vp-p conditions ? 320 i shdn power-supply current in shutdown ? 500 600 i dd power-supply current (note 5) v 2.7 3.6 v dd power-supply voltage (note 5) nv-s 5 digital feedthrough ms 2 time required to exit shutdown ? -0.1 0 0.1 current into fb ? 20 output settling time v 0 to v dd output voltage swing (note 4) units min typ max symbol parameter i sink = 2ma v 0.13 0.4 v ol output low voltage i source = 2ma v v dd - 0.5 v oh output high voltage v in = 0 or v dd ? -1 0.001 1 i in input leakage current pf 8 c in input capacitance v/? 0.6 sr voltage output slew rate timing characteristics?ax5132 (+5v) (v dd = +5v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, output amplifier connect- ed in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) ns 40 t css cs fall to sclk rise setup time ns 40 t cl sclk pulse width low conditions ns 100 t cp sclk clock period ns 40 t ch sclk pulse width high ns 0 t csh sclk rise to cs rise hold time ns 10 t cs0 sclk rise to cs fall delay time ns 40 t ds sdi setup time ns 0 t dh sdi hold time units min typ max symbol parameter ns 100 t csw cs pulse width high ns 40 t cs1 cs rise to sclk rise hold time c load = 200pf ns 80 t do1 sclk rise to dout valid propagation delay time c load = 200pf ns 80 t do2 sclk fall to dout valid propagation delay time digital outputs power requirements dynamic performance
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference _______________________________________________________________________________________ 5 note 1: accuracy is guaranteed by following the table: note 2: offset is measured at the code closest to 10mv. note 3: the temperature coefficient is determined by the ?ox?method in which the maximum d v out over the temperature range is divided by d t and the typical reference voltage. note 4: accuracy is better than 1.0lsb for v out = 10mv to v dd - 180mv. guaranteed by psr test on end points. note 5: r load = and digital inputs are at either v dd or dgnd. timing characteristics?ax5133 (+3v) (v dd = +3v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, output amplifier connect- ed in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) ns 60 t css cs fall to sclk rise setup time ns 150 ns c load = 200pf 75 t csw t cl sclk pulse width low conditions ns 150 t cp sclk clock period ns 75 t ch sclk pulse width high ns 0 t csh sclk rise to cs rise hold time cs pulse width high ns 75 t cs1 cs rise to sclk rise hold time c load = 200pf ns 200 t do1 sclk rise to dout valid propagation-delay time ns 200 t do2 sclk fall to dout valid propagation-delay time ns 10 t cs0 sclk rise to cs fall delay time ns 60 t ds sdi setup time ns 0 t dh sdi hold time units min typ max symbol parameter 32 5 65 3 8191 8191 accuracy guaranteed to code: from code: v dd (v)
200 250 300 350 400 450 500 -60 -20 -40 0 20406080100 max5132 supply current vs. temperature max5132/33 toc04 temperature (?) supply current ( m a) (code = 1555 hex) (code = 0000 hex) 250 300 400 350 450 500 4 4.5 5 5.5 6 max5132 supply current vs. supply voltage max5132/33 toc05 supply voltage (v) supply current ( m a) (code = 1555 hex) (code = 0000 hex) 0 0.5 1.0 1.5 2.0 2.5 3.0 -60 -20 -40 0 20406080100 max5132 shutdown current vs. temperature max5132/33 toc06 temperature (?) shutdown current ( m a) 2.490 2.495 2.500 2.505 2.510 -60 -20 -40 0 20406080100 max5132 full-scale output voltage vs. temperature max5132/33 toc07 temperature (?) full-scale output (v) r l = 5k w c l = 100pf 0.1 1 10 100 max5132 full-scale output error vs. resistive load max5132/33 toc08 r l (k w ) full-scale output error (lsb) -3.50 -2.75 -2.00 -1.25 -0.50 0.25 cs 5v/div out 1v/div 2 m s/div max5132 dynamic-response rise time max5132/33-09 max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference 6 _______________________________________________________________________________________ typical operating characteristics (v dd = +5v, r l = 5k , c l = 100pf, os = agnd, t a = +25?, output amplifier connected in unity-gain configuration, unless other- wise noted.) -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 2,000 4,000 6,000 8,000 10,000 max5132 integral nonlinearity vs. digital input code max5132/33 toc01 digital input code inl (lsb) -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 2,000 4,000 6,000 8,000 10,000 max5132 differential nonlinearity vs. digital input code max5132/33 toc02 digital input code dnl (lsb) 2.490 2.495 2.500 2.505 2.510 -60 -20 20 60 -40 0 40 80 100 max5132 reference voltage vs. temperature max5132/33 toc03 temperature (?) reference voltage (v)
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v dd = +5v, r l = 5k , c l = 100pf, os = agnd, t a = +25?, output amplifier connected in unity-gain configuration,unless other- wise noted.) cs 5v/div out 1v/div 2 m s/div max5132 dynamic-response fall time max5132/33-10 sclk 2v/div out 1mv/div ac-coupled 2 m s/div max5132 digital feedthrough (sclk, out) max5132/33-11 cs 2v/div out 100mv/div ac-coupled 5 m s/div max5132 major carry transition max5132/33-12 -0.20 -0.15 -0.10 0 -0.05 0.05 0.10 0.15 0.20 0.25 0 2,000 4,000 6,000 8,000 10,000 max5133 integral nonlinearity vs. digital input code max5132/33 toc13 digital input code inl (lsb) -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0 2,000 4,000 6,000 8,000 10,000 max5133 differential nonlinearity vs. digital input code max5132/33 toc14 digital input code dnl (lsb) 1.240 1.245 1.250 1.255 1.260 -60 -20 20 60 -40 0 40 80 100 max5133 reference voltage vs. temperature max5132/33 toc15 temperature (?) reference voltage (v) 200 250 300 350 400 -60 -20 -40 0 20406080100 max5133 supply current vs. temperature max5132/33 toc16 temperature (?) supply current ( m a) (code = 1555 hex) (code = 0000 hex) 200 300 250 350 400 2.5 2.75 3.0 3.25 3.5 max5133 supply current vs. supply voltage max5132/33 toc17 supply voltage (v) supply current ( m a) (code = 1555 hex) (code = 0000 hex) 0.1 0.2 0.3 0.4 0.5 -60 -20 -40 0 20406080100 max5133 shutdown current vs. temperature max5132/33 toc18 temperature (?) shutdown current ( m a)
cs 2v/div out 400mv/div 1 m s/div max5132 dynamic-response fall time max5132/33-22 sclk 2v/div out 500mv/div ac-coupled 2 m s/div max5133 digital feedthrough (sclk, out) max5132/33-23 cs 2v/div out 100mv/div ac-coupled 5 m sv/div max5133 major carry transition max5132/33-24 max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference 8 _______________________________________________________________________________________ 1.240 1.245 1.250 1.255 1.260 -60 -20 -40 0 20406080100 max5133 full-scale output voltage vs. temperature max5132/33 toc19 temperature (?) full-scale output (v) 0.1 10 100 1000 max5133 full-scale output error vs. resistive load max5132/33 toc20 r l (k w ) full-scale output error (lsb) -4 -3 -2 -1 0 cs 2v/div out 400mv/div 1 m s/div max5133 dynamic-response rise time max5132/33-21 typical operating characteristics (continued) (v dd = +5v, r l = 5k , c l = 100pf, os = agnd, t a = +25?, output amplifier connected in unity-gain configuration,unless other- wise noted.)
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference _______________________________________________________________________________________ 9 pin description name function 1 fb amplifier inverting sense input (analog input) pin 2 out analog output voltage. high impedance if part is in shutdown. 3 rstval reset value input (digital input) 1: connect to vdd to select midscale as the output reset value. 0: connect to dgnd to select 0v as the output reset value. 4 pdl power-down lockout (digital input). 1: normal operation. 0: disallows shutdown (device cannot be powered down). 5 clr reset dac input (digital input). clears the dac to its predetermined (rstval) output state. clearing the dac will cause it to exit a software shutdown state. 6 cs active-low chip-select input (digital input) 7 din serial data input. data is clocked in on the rising edge of sclk. 8 sclk serial clock input 9 dgnd digital ground 10 dout serial data output 11 upo user-programmable output (digital output) 12 pd power-down input (digital input). pulling pd high when pdl = v dd places the ic into shutdown with a maximum shutdown current of 20?. 13 agnd analog ground 14 ref buffered reference output/input. in internal reference mode, the reference buffer provides a +2.5v (max5132) or +1.25v (max5133) nominal output, externally adjustable at refadj. in external reference mode, disable the internal reference by pulling refadj to v dd and applying the external reference to ref. 15 refadj analog reference adjust input. bypass with a 33nf capacitor to agnd. connect to v dd when using an external reference. 16 v dd positive power supply. bypass with a 0.1? capacitor in parallel with a 4.7? capacitor to agnd.
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference 10 ______________________________________________________________________________________ _______________detailed description the max5132/max5133 13-bit, force/sense dacs are easily configured with a 3-wire serial interface. they include a 16-bit data-in/data-out shift register and have a double-buffered digital input consisting of an input regis- ter and a dac register. in addition, these devices employ precision bandgap references, as well as an out- put amplifier with accessible feedback and output pins that can be used for setting the gain externally (figure 1) or for forcing and sensing applications. these dacs are designed with an inverted r-2r ladder network (figure 2) that produces a weighted voltage proportion- al to the digital input code. internal reference both devices use an on-board precision bandgap ref- erence with a low temperature coefficient of only 10ppm/? (max) to generate an output voltage of +2.5v (max5132) or +1.25v (max5133). the ref pin can source up to 100? and may become unstable with capacitive loads exceeding 100pf. refadj can be used for minor adjustments to the reference voltage. the circuits in figures 3a and 3b achieve a nominal ref- erence adjustment range of ?%. connect a 33nf capacitor from refadj to agnd to establish low-noise max5132 max5133 sr control 16-bit shift register decode control input register bandgap reference reference buffer dac register dac 2x (x1) dout upo out fb 13 4k 1.25v agnd dgnd v dd din sclk cs 2.5v (1.25v) logic output clr pdl pd rstval refadj ( ) for max5133 only. ref figure 1. simplified functional diagram out fb shown for all 1s on dac d0 d10 d11 d12 *internal reference: 2.5v (max5132), 1.25v (max5133); or external reference 2r 2r 2r 2r 2r rrr ref* agnd figure 2. simplified inverted r-2r dac structure
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference ______________________________________________________________________________________ 11 operation of the dac. larger capacitor values may be used but will result in increased start-up delay. the time constant t for the start-up delay is determined by the refadj input impedance of 4k and c refadj : t = 4k c refadj external reference an external reference may be applied to the ref pin. disable the internal reference by pulling refadj to v dd . this allows an external reference signal (ac- or dc-based) to be fed into the ref pin. for proper oper- ation, do not exceed the input voltage range limits of 0v to (v dd - 1.4v) for v ref . determine the output voltage using the following equa- tion (refadj = v dd ): v out = v ref (nb / 8192)g where nb is the numeric value of the max5132/ max5133 input code (0 to 8191), v ref is the external reference voltage, and g is the gain of the output amplifier, set by an external resistor-divider. the ref pin has a minimum input resistance of 40k and is code dependent. output amplifier the max5132/max5133? dac output is internally buffered by a precision amplifier with a typical slew rate of 0.6v/?. access to the output amplifier? inverting input (fb) provides the user greater flexibility with amplifier gain setting and signal conditioning (see applications information ). the output amplifier typically settles to ?.5lsb from a full-scale transition within 20? when it is connected in unity gain and loaded with 5k ?? 100pf. loads less than 1k may result in degraded performance. power-down mode the max5132/max5133 feature software- and hard- ware-programmable (pd pin) shutdown modes that reduce the typical supply current to 3?. to enter soft- ware shutdown mode, program the control sequence for the dac as shown in table 1. in shutdown mode, the amplifier output becomes high impedance and the serial interface remains active. data in the input registers is saved, allowing the max5132/max5133 to recall the output state prior to entering shutdown when returning to normal operation. to exit shutdown mode, load both input and dac regis- ters simultaneously or update the dac register from the input register. when returning from shutdown to normal operation, wait 2ms for the reference to settle. when using an external reference, the dac requires only 20? for the output to stabilize. power-down lockout input ( pdl ) the power-down lockout ( pdl ) pin disables shutdown when low. when in shutdown mode, a high-to-low tran- sition on pdl will wake up the dac with its output still set to the state prior to power-down. pdl can also be used to wake up the device asynchronously. power-down input (pd) pulling pd high places the max5132/max5133 in shut- down. pulling pd low will not return the max5132/ max5133 to normal operation. a high-to-low transition on pdl or appropriate commands (table 1) via the ser- ial interface are required to exit power-down. refadj +3v 15k 100k 400k 33nf max5133 refadj +5v 90k 100k 400k 33nf max5132 figure 3a. max5132 reference adjust circuit figure 3b. max5133 reference adjust circuit
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference 12 ______________________________________________________________________________________ serial-interface configuration (spi/qspi/microwire/pic16/pic17) the max5132/max5133 3-wire serial interface is com- patible with spi, qspi, pic16/pic17 (figure 4) and microwire (figure 5) interface standards. the 2- byte-long serial input word contains three control bits and 13 data bits in msb-first format (table 2). the max5132/max5133? digital inputs are double buffered, which allows the user to: load the input register without updating the dac register, update the dac register with data from the input register, update the input and dac registers concurrently. the 16-bit input word may be sent in two 1-byte pack- ets (spi-, microwire- and pic16/pic17-compatible), with cs low during this period. the control bits c2, c1, and c0 (table 1) determine: the clock edge on which dout transitions, the state of the user-programmable logic output, the configuration of the device after shutdown. the general timing diagram in figure 6 illustrates how data is acquired. cs must be low for the part to receive data. with cs low, data at din is clocked into the regis- ter on the rising edge of sclk. when cs transitions high, data is latched into the input and/or dac registers, depending on the setting of the three control bits c2, c1, and c0. the maximum serial-clock frequency guar- anteed for proper operation is 10mhz for the max5132 and 6.6mhz for the max5133. figure 7 depicts a more detailed timing diagram of the serial interface. table 1. serial-interface programming commands x = don? care din sclk cs mosi sck i/o spi/qspi port (pic16/pic17) ss v dd cpol = 0, cpha = 0 (cke = 1, ckp = 0, smp = 0, sspm3 - sspmo = 0001) ( ) pic16/pic17 only max5132 max5133 figure 4. spi/qspi interface connections (pic16/pic17) din sclk cs sk so i/o microwire port max5132 max5133 figure 5. microwire interface connections d12 ............... d0 function c2 c0 c1 1 1 1 00xxxxxxxxxxx mode 0: dout clocked out on sclk? falling edge (default). 1 xxxxxxxxxxxxx shutdown dac (provided pdl = 1). 16-bit serial word 0 xxxxxxxxxxxxx no operation. 1 xxxxxxxxxxxxx upo goes high. 0 1 1 1 1 1xxxxxxxxxxxx mode 1: dout clocked out on sclk? rising edge. 1 0 0 0 1 xxxxxxxxxxxxx upo goes low (default). 0 13-bit dac data simultaneously load input and dac registers; exit shutdown. 0 1 1 1 0 xxxxxxxxxxxxx update dac register from input register; exit shutdown. 0 1 0 0 0 13-bit dac data load input register; dac register unchanged.
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference ______________________________________________________________________________________ 13 pic16 with ssp module and pic17 interface the max5132/max5133 are compatible with a pic16/pic17 microcontroller (?), using the synchro- nous serial port (ssp) module. to establish spi com- munication, connect the controller as shown in figure 4 and configure the pic16/pic17 as system master by initializing its synchronous serial-port control register (sspcon) and synchronous serial-port status register (sspstat) to the bit patterns shown in tables 3 and 4. in spi mode, the pic16/pic17 ?s allow eight bits of data to be synchronously transmitted and received simultaneously. two consecutive 8-bit writings (figure 6) are necessary to feed the dac with three control bits and 13 data bits. din data transitions on the serial clock? falling edge and is clocked into the dac on sclk? rising edge. the first eight bits of din contain the three control bits (c2, c1, c0) and the first five data bits (d12?8). the second 8-bit data stream contains the remaining bits, d7?0. serial data output the contents of the internal shift-register are output seri- ally on dout, which allows for daisy-chaining (see applications information ) of multiple devices as well as data readback. the max5132/max5133 may be pro- grammed to shift data out of dout on the serial clock? rising edge (mode 1) or on the falling edge (mode 0). the latter is the default during power-up and provides a lag of 16 clock cycles, maintaining spi, qspi, microwire, and pic16/pic17 compatibility. in mode 1, the output data lags din by 15.5 clock cycles. during power-down, dout retains its last digital state prior to shutdown. user-programmable output (upo) the upo feature allows an external device to be con- trolled through the serial-interface setup (table 1), thereby reducing the number of microcontroller i/o ports required. during power-down, this output will retain the last digital state before shutdown. with clr pulled low, upo will reset to the default state after wake-up. cs sclk din command executed 9 8 16 1 c1 c2 d0 c0 d12 d11 d10 d9 d6 d5 d4 d3 d2 d1 d8 d7 figure 6. serial-interface timing sclk din dout t cs0 t css t cl t ch t cp t csw t cs1 t csh t ds t do1 t do2 t dh cs figure 7. detailed serial-interface timing table 2. serial data format c2, c1, c0 d12................................d0 16 bits of serial data t msb ........................................... lsb msb ..... data bits ..... lsb control bits
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference 14 ______________________________________________________________________________________ __________applications information definitions integral nonlinearity (inl) integral nonlinearity (figure 8a) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer func- tion, once offset and gain errors have been nullified. for a dac, the deviations are measured at every single step. differential nonlinearity (dnl) differential nonlinearity (figure 8b) is the difference between an actual step height and the ideal value of 1lsb. if the magnitude of the dnl is less than or equal to 1lsb, the dac guarantees no missing codes and is monotonic. offset error the offset error (figure 8c) is the difference between the ideal and the actual offset point. for a dac, the off- set point is the step value when the digital input is zero. this error affects all codes by the same amount and can usually be compensated for by trimming. table 3. detailed sspcon register contents x = don? care table 4. detailed sspstat register contents x = don? care sspm3 0 synchronous serial-port mode select bit. sets spi master mode and selects f clk = f osc / 16. max5132/max5133 settings synchronous serial-port control register (sspcon) wcol x write-collision detection bit sspm1 0 control bit bit1 bit0 sspm0 1 bit3 bit2 sspm2 0 sspen 1 synchronous serial port enable bit 0: disables serial port and configures these pins as i/o port pins. 1: enables serial port and configures sck, sdo, and sci as seri- al-port pins. bit5 bit4 ckp 0 clock-polarity select bit. ckp = 0 for spi master-mode selection. bit7 bit6 sspov x receive-overflow detection bit s x start bit max5132/max5133 settings synchronous serial-port status register (sspstat) smp 0 spi data-input sample phase. input data is sampled at the mid- dle of the data-output time. ua x control bit bit1 bit0 bf x bit3 bit2 r/w x d/a x data-address bit bit5 bit4 p x stop bit read/write bit information update address bit7 buffer full-status bit bit6 cke 1 spi clock-edge select bit. data will be transmitted on the rising edge of the serial clock.
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference ______________________________________________________________________________________ 15 gain error gain error (figure 8d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corre- sponds to the same percentage error in each step. settling time the settling time is the amount of time required from the start of a transition until the dac output settles to its new output value within the converter? specified accuracy. digital feedthrough digital feedthrough is noise generated on the dac? output when any digital input transitions. proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the dac itself. unipolar output figure 9 shows the max5132/max5133 setup for unipolar, rail-to-rail operation with a closed-loop gain of 2v/v. with its internal reference of +2.5v, the max5132 provides a convenient unipolar output range of 0 to +4.99939v, while the max5133 offers an output range of 0 to +2.499695v with its on-board +1.25v ref- erence. table 5 lists example codes for unipolar output voltages. bipolar output the max5132/max5133 can be configured for unity- gain bipolar operation (fb = out) using the circuit shown in figure 10. the output voltage v out is then given by the following equation: v out = v ref [g (nb / 8192) - 1] 0 2 1 4 3 7 6 5 000 010 001 011 100 101 110 at step 011 (1/2 lsb ) at step 001 (1/4 lsb ) 111 digital input code analog output value (lsb) figure 8a. integral nonlinearity figure 8b. differential nonlinearity 0 2 1 4 3 6 5 000 010 001 011 100 101 differential linearity error (-1/4 lsb) differential linearity error (+1/4 lsb) 1 lsb 1 lsb digital input code analog output value (lsb) 0 2 1 3 000 010 001 011 actual diagram ideal diagram actual offset point offset error (+1 1/4 lsb) ideal offset point digital input code analog output value (lsb) figure 8c. offset error figure 8d. gain error 0 5 4 6 7 000 101 100 110 111 ideal diagram gain error (-1 1/4 lsb) ideal full-scale output actual full-scale output digital input code analog output value (lsb) rail-to-rail is a registered trademark of nippon motorola, ltd.
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference 16 ______________________________________________________________________________________ where nb is the numeric value of the dac? binary input code, v ref is the voltage of the internal (or exter- nal) precision reference, and g is the overall gain. the application circuit in figure 10 uses a low-cost op amp (max4162) external to the max5132/max5133. together with the max5132/max5133, this circuit offers an overall gain of 2v/v. table 6 lists example codes for bipolar output voltages. reset (rstval) and clear ( c c l l r r ) functions the max5132/max5133 dacs feature a clear pin ( clr ), which resets the output to a certain value, depending upon how rstval is set. rstval = dgnd selects an output of 0, and rstval = v dd selects a midscale output when clr is pulled low. the clr pin has a minimum input resistance of 40k in series with a diode to the supply voltage (v dd ). if the digital voltage is higher than the supply voltage for the part, a small input current may flow, but this current will be limited to (v clr - v dd - 0.5v) / 40k . note: clearing the dac will also cause the part to exit software shutdown (pd = 0). daisy-chaining devices any number of max5132/max5133s may be daisy- chained simply by connecting the serial data output pin (dout) of one device to the serial data input pin (din) of the following device in the chain (figure 11). another configuration (figure 12) allows several max5132/max5133 dacs to share one common din signal line. in this configuration, the data bus is com- mon to all devices; data is not shifted through a daisy chain. however, more i/o lines are required in this con- figuration because each ic needs a dedicated cs line. max5132 max5133 dac gain = 2 v/v ref fb out dgnd agnd +5v/+3v v dd 50k 50k figure 9. unipolar output circuit using internal (+1.25v/+2.5v) or external reference. with external reference, pull refadj to v dd . figure 10. unity-gain bipolar output circuit using internal (+1.25v/+2.5v) or external reference. with external reference, pull refadj to v dd . agnd dgnd max5132 max5133 dac ref fb out 50k 50k v- v+ v dd v out +5v/+3v max4162 to other serial devices max5132 max5133 din sclk cs max5132 max5133 max5132 max5133 din dout dout dout sclk cs i ii iii din sclk cs figure 11. daisy-chaining multiple devices with the digital i/os din/dout
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference ______________________________________________________________________________________ 17 table 5. unipolar code table (gain = +2v/v) table 6. bipolar code table for figure 10 to other serial devices max5132 max5133 din sclk cs max5132 max5133 din sclk cs max5132 max5133 din i ii iii sclk cs din sclk cs1 cs2 cs3 figure 12. multiple devices share one common digital input (din) dac contents external reference max5132/max5133 max5133 max5132 msb lsb internal reference 0 0000 0000 0001 v ref (1 / 8192) 2 analog output 1 1111 1111 1111 v ref (8191 / 8192) 2 305.18? 0v 610.35? 0v 0 0000 0000 0000 0v 1 0000 0000 0000 v ref (4096 / 8192) 2 1.25v 1.24969v 2.5v 2.49939v 0 1111 1111 1111 v ref (4095 / 8192) 2 2.49969v 1.25031v 4.99939v 2.50061v 1 0000 0000 0001 v ref (4097 / 8192) 2 max5132/max5133 dac contents internal reference 0 0000 0000 0001 v ref [ 2 (1 / 8192) - 1] analog output 1 1111 1111 1111 v ref [2 (8191 / 8192) - 1] external reference -1.24969v -1.25v -2.49939v -2.5v 0 0000 0000 0000 -v ref max5133 1 1000 0000 0000 v ref [2 (4096 / 8192) - 1] max5132 0v -305.18? 0v -610.35? 0 1111 1111 1111 v ref [2 (4095 / 8192) - 1] msb lsb 1.24969v 305.18? 2.49939v 610.35? 1 1000 0000 0001 v ref [2 (4097 / 8192) - 1]
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference 18 ______________________________________________________________________________________ dac out max5132 max5133 10k 26k fb ref v dd dgnd agnd +5v/ +3v ac reference input 500mvp-p max495 +5v/+3v figure 13. external reference with ac components using an external reference with ac components the max5132/max5133 have multiplying capabilities within the reference input voltage range specifications. figure 13 shows a technique for applying a sinusoidal input to ref, where the ac signal is offset before being applied to the reference input. power-supply and bypassing considerations on power-up, the input and dac registers are cleared to either zero (rstval = dgnd) or midscale (rstval = v dd ). bypass the power supply (v dd ) with a 4.7? capacitor in parallel with a 0.1? capacitor to agnd. minimize lead lengths to reduce lead inductance. layout considerations digital and ac signals coupling to agnd can create noise at the output. connect agnd to the highest quali- ty ground available. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. wire-wrapped boards and sockets are not recommended. if noise becomes an issue, shield- ing may be required. ___________________chip information transistor count: 3308 substrate connected to agnd.
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference ______________________________________________________________________________________ 19 ________________________________________________________package information qsop.eps
max5132/max5133 +5v/+3v, 13-bit, serial, force/sense dacs with 10ppm/? internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes

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